7. Clock Signals

7.3 Phase-Locked-Loop


The processor uses the internal PLL for clock generation and multiplication as shown in Figure 7-1.

Values of the termination resistors for the SysClkRet/SysClkRet* signals are system-dependent. The system designer must select a value based upon the characteristic impedance of the board, therefore it is beyond the scope of this manual to specify values for these termination resistors.



Figure 7-1 R10000 System and Secondary Cache Clock Interface




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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